View 8XC152JA_6096598.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. october 1989 copyright ? intel corporation, 1995 order number: 270431-003 8XC152JA/jb/jc/jd universal communication controller 8-bit microcontroller x 8k factory mask programmable rom available y superset of 80c51 architecture y multi-protocol serial communication i/o port (2.048 mbps/2.4 mbps max) e sdlc/hdlc only e csma/cd and sdlc/hdlc e user definable protocols y full duplex/half duplex y mcs -51 compatible uart y 16.5 mhz maximum clock frequency y multiple power conservation modes y 64kb program memory addressing y 64kb data memory addressing y 256 bytes on-chip ram y dual on-chip dma channels y hold/hold acknowledge y two general purpose timer/counters y 5 or 7 i/o ports y 56 special function registers y 11 interrupt sources y available in 48 pin dual-in-line package and 68 pin surface mount plcc package (see packaging spec. order y 231369) the 80c152, which is based on the mcs -51 cpu, is a highly integrated single-chip 8-bit microcontroller designed for cost-sensitive, high-speed, serial communications. it is well suited for implementing integrated services digital networks (isdn), emerging local area networks, and user defined serial backplane applica- tions. in addition to the multi-protocol communication capability, the 80c152 offers traditional microcontroller features for peripheral i/o interface and control. silicon implementations are much more cost effective than multi-wire cables found in board level parallel-to- serial and serial-to-parallel converters. the 83c152 contains, in silicon, all the features needed for the serial- to-parallel conversion. other 83c152 benefits include: 1) better noise immunity through differential signaling or fiber optic connections, 2) data integrity utilizing the standard, designed in crc checks, and 3) better modulari- ty of hardware and software designs. all of theseecost, network parameter and real estate improvementse apply to 83c152 serial links between boards or systems and 83c152 serial links on a single board.
8XC152JA/jb/jc/jd 270431 1 270431 2 270431 3 figure 1. connection diagrams 2
8XC152JA/jb/jc/jd * on 80c152jb/jd only 270431 18 figure 2. block diagram 3
8XC152JA/jb/jc/jd 80c152jb/jd general description the 80c152jb/jd is a romless extension of the 80c152 universal communication controller. the 80c152jb has the same five 8-bit i/o ports of the 80c152, plus an additional two 8-bit i/o ports, port 5 and port 6. the 80c152jb/jd also has two addi- tional control pins, eben ( e prom b us en able), and epsen ( e prom bus p rogram s tore en able). eben selects the functionality of port 5 and port 6. when eben is low, these ports are strictly i/o, simi- lar to port 4. the sfr location for port 5 is 91h and port 6 is 0a1h. this means port 5 and port 6 are not bit addressable. with eben low, all program memo- ry fetches take place via port 0 and port 2. (the 80c152 is a romless only product). when eben is high, port 5 and port 6 form an address/data bus called the e-bus (eprom-bus) for program memory operations. epsen is used in conjunction with port 5 and port 6 program memory operations. epsen functions like psen during program memory operation, but sup- ports port 5 and port 6. epsen is the read strobe to external program memory for port 5 and port 6. epsen is activated twice during each machine cycle unless an external data memory operation occurs on port(s) 0 and port 2. when external data memory is accessed the second activation of epsen is skipped, which is the same as when using psen . note that data memory fetches cannot be made through ports 5 and 6. when eben is high and ea is low, all program mem- ory operations take place via ports 5 and 6. the high byte of the address goes out on port 6, and the low byte is output on port 5. ale is still used to latch the address on port 5. next, the op code is read on port 5. the timing is the same as when using ports 0 and 2 for external program memory operations. table 1. program memory fetches eben ea program psen epsen comments fetch via 0 0 p0, p2 active inactive addresses 0 0ffffh 0 1 n/a n/a n/a invalid combination 1 0 p5, p6 inactive active addresses 0 0ffffh 1 1 p5, p6 inactive active addresses 0 1fffh p0, p2 active inactive addresses t 2000h table 2. 8xc152 product differences romless csma/cd hdlc/sdlc rom plcc plcc 5 i/o 7 i/0 version and only version and only ports ports hdlc/sdlc available dip 80c152ja ** (83c152ja) ** 80c152jb *** 80c152jc ** (83c152jc) ** 80c152jd *** notes: * e options available 0 standard frequency range 3.5 mhz to 12 mhz 0`` b 1'' frequency range 3.5 mhz to 16.5 mhz 4
8XC152JA/jb/jc/jd pin y pin description dip plcc (1) 48 2 v cc esupply voltage. 24 3,33 (2) v ss ecircuit ground. 18-21, 27-30, port 0 eport 0 is an 8-bit open drain bidirectional i/o port. as an output port each pin 25-28 34-37 can sink 8 ls ttl inputs. port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program memory if eben is pulled low. during accesses to external data memory, port 0 always emits the low-order address byte and serves as the multiplexed data bus. in these applications it uses strong internal pullups when emitting 1s. port 0 also outputs the code bytes during program verification. external pullups are required during program verification. 1-8 4-11 port 1 eport 1 is an 8-bit bidirectional i/o port with internal pullups. port 1 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (i il , on the data sheet) because of the internal pullups. port 1 also serves the functions of various special features of the 8xc152, as listed below: pin name alternate function p1.0 grxd gsc data input pin p1.1 gtxd gsc data output pin p1.2 den gsc enable signal for an external driver p1.3 txc gsc input pin for external transmit clock p1.4 rxc gsc input pin for external receive clock p1.5 hld dma hold input/output p1.6 hlda dma hold acknowledge input/output 29-36 41-48 port 2 eport 2 is an 8-bit bidirectional i/o port with internal pullups. port 2 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (i il , on the data sheet) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program memory if eben is pulled low. during accesses to external data memory that use 16- bit addresses (movx @ dptr and dma operations), port 2 emits the high-order address byte. in these applications it uses strong internal pullups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ ri), port 2 emits the contents of the p2 special function register. port 2 also receives the high-order address bits during program verification. 10- 17 14-16, port 3 eport 3 is an 8-bit bidirectional i/o port with internal pullups. port 3 pins that 18, 19, have 1s written to them are pulled high by the internal pullups, and in that state can be 23-25 used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (i il , on the data sheet) because of the pullups. port 3 also serves the functions of various special features of the mcs-51 family, as listed below: pin name alternate function p3.0 rxd serial input line p3.1 txd serial output line p3.2 int0 external interrupt 0 p3.3 int1 external interrupt 1 p3.4 t0 timer 0 external input p3.5 t1 timer 1 external input p3.6 wr external data memory write strobe p3.7 rd external data memory read strobe 5
8XC152JA/jb/jc/jd pin description (continued) pin y pin description 47-40 65-58 port 4 eport 4 is an 8-bit bidirectional i/o port with internal pullups. port 4 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 4 pins that are externally being pulled low will source current (i il , on the data sheet) because of the internal pullups. in addition, port 4 also receives the low-order address bytes during program verification. 913 rst ereset input. a logic low on this pin for three machine cycles while the oscillator is running resets the device. an internal pullup resistor permits a power-on reset to be generated using only an external capacitor to v ss . although the gsc recognizes the reset after three machine cycles, data may continue to be transmitted for up to 4 machine cycles after reset is first applied. 38 55 ale eaddress latch enable output signal for latching the low byte of the address during accesses to external memory. in normal operation ale is emitted at a constant rate of (/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory. while in reset, ale remains at a constant high level. 37 54 psen eprogram store enable is the read strobe to external program memory. when the 8xc152 is executing from external program memory, psen is active (low). when the device is executing code from external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. while in reset, psen remains at a constant high level. 39 56 ea eexternal access enable. ea must be externally pulled low in order to enable the 8xc152 to fetch code from external program memory locations 0000h to 0fffh. ea must be connected to v cc for internal program execution. 23 32 xtal1 einput to the inverting oscillator amplifier and input to the internal clock generating circuits. 22 31 xtal2 eoutput from the inverting oscillator amplifier. n/a 17, 20 port 5 eport 5 is an 8-bit bidirectional i/o port with internal pullups. port 5 pins that 21, 22 have 1s written to them are pulled high by the internal pullups, and in that state can 38, 39 be used as inputs. as inputs, port 5 pins that are externally being pulled low will 40, 49 source current (i il , on the data sheet) because of the internal pullups. port 5 is also the multiplexed low-order address and data bus during accesses to external program memory if eben is pulled high. in this application it uses strong pullups when emitting 1s. n/a 67, 66 port 6 eport 6 is an 8-bit bidirectional i/o port with internal pullups. port 6 pins that 52, 57 have 1s written to them are pulled high by the internal pullups, and in that state can 50, 68 be used as inputs. as inputs, port 6 pins that are externally pulled low will source 1, 51 current (i il , on the data sheet) because of the internal pullups. port 6 emits the high-order address byte during fetches from external program memory if eben is pulled high. in this application it uses strong pullups when emitting 1s. n/a 12 eben ee-bus enable input that designates whether program memory fetches take place via ports 0 and 2 or ports 5 and 6. table 1 shows how the ports are used in conjunction with eben. n/a 53 epsen ee-bus program store enable is the read strobe to external program memory when eben is high. table 2 shows when epsen is used relative to psen depending on the status of eben and ea . 6
8XC152JA/jb/jc/jd oscillator characteristics xtal1 and xtal2 are the input and output, respec- tively, of an inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in figure 3. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left uncon- nected, as shown in figure 4. there are no require- ments on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. an external oscillator may encounter as much as a 100 pf load at xtal1 when it starts-up. this is due to interaction between the amplifier and its feedback capacitance. once the external signal meets the v il and v ih specifications the capacitance will not ex- ceed 20 pf. 270431 5 figure 3. using the on-chip oscillator 270431 6 figure 4. external clock drive idle mode in idle mode, the cpu puts itself to sleep while most of the on-chip peripherals remain active. the major peripherals that do not remain active during idle, are the dma channels. the idle mode is invoked by software. the content of the on-chip ram and all the special function registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. power down mode in power down mode, the oscillator is stopped and all on-chip functions cease except that the on-chip ram contents are maintained. the mode power down is invoked by software. the power down mode can be terminated only by a hardware reset. table 3. status of the external pins during idle and power down modes 80c152ja/83c152ja/80c152jc/83c152jc mode program ale psen port 0 port 1 port 2 port 3 port 4 memory idle internal 1 1 data data data data data idle external 1 1 float data address data data power down internal 0 0 data data data data data power down external 0 0 2 float data data data data 80c152jb/80c152jd mode instruction ale psen epsen port 0 port 1 port 2 port 3 port 4 port 5 port 6 bus idle p0, p2 1 1 1 float data address data data 0ffh 0ffh idle p5, p6 1 1 1 data data data data data 0ffh address power down p0, p2 0 0 1 float data data data data 0ffh 0ffh power down p5, p6 0 1 2 0 data data data data data 0ffh 0ffh note: for more detailed information on the reduced power modes refer to the embedded controller handbook, and application note ap-252, ``designing with the 80c51bh.'' 2 note difference of logic level of psen during power down for rom ja/jc and rom emulation mode for jc/jd. 7
8XC152JA/jb/jc/jd absolute maximum ratings * ambient temperature under bias 0 cto a 70 c storage temperature b 65 cto a 150 c voltage on any pin to v ss b 0.5v to (v cc a 0.5v) voltage on v cc to vss b 0.5v to a 6.5v power dissipation 1.0w (9) notice: this data sheet contains preliminary infor- mation on new products in production. the specifica- tions are subject to change without notice. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. d.c. characteristics (t a e 0 cto a 70 c; v cc e 5v g 10%; v ss e 0v) symbol parameter min typ max unit test conditions (note 3) v il input low voltage b 0.5 0.2v cc b 0.1 v (all except ea , eben) v il1 input low voltage b 0.5 0.2v cc b 0.3 v (ea , eben) v ih input high voltage 0.2v cc a 0.9 v cc a 0.5 v (except xtal1, rst ) v ih1 input high voltage 0.7v cc v cc a 0.5 v (xtal1, rst ) v ol output low voltage 0.45 v i ol e 1.6 ma (ports 1, 2, 3, 4, 5, 6) (note 4) v ol1 output low voltage 0.45 v i ol e 3.2 ma (port 0, ale, psen , epsen ) (note 4) v oh output high voltage 2.4 v i oh eb 60 m a (ports 1, 2, 3, 4, 5, 6 comm9 v cc e 5v g 10% ale, psen , epsen ) 0.9v cc vi oh eb 10 m a v oh1 output high voltage 2.4 v i oh eb 400 m a (port 0 in external v cc e 5v g 10% bus mode) 0.9v cc vi oh eb 40 m a (note 5) i il logical 0 input b 50 m av in e 0.45v current (ports 1, 2, 3, 4, 5, 6) i tl logical 1 to 0 b 650 m av in e 2v transition current (ports 1, 2, 3, 4, 5, 6) i li input leakage g 10 m a 0.45 k v in k v cc (port 0, ea ) rrst reset pullup resistor 40 k x i ih logical 1 input current (eben) a 60 m a i cc power supply current : active (16.5 mhz) 31 41.1 ma (note 6) idle (16.5 mhz) 8 15.4 ma (note 6) power down mode 10 m av cc e 2.0v to 5.5v 8
8XC152JA/jb/jc/jd max i cc (active) e (2.24 c freq) a 4.16 (note 6) max i cc (idle) e (0.8 c freq) a 2.2 (note 6) 270431 7 figure 5. i cc vs frequency explanation of the ac symbols each timing symbol has 5 characters. the first char- acter is always a `t' (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a: address. c: clock d: input data. h: logic level high. i: instruction (program memory contents). l: logic level low, or ale. p: psen . q: output data. r: read signal. t: time. v: valid. w: write signal. x: no longer a valid logic level. z: float. for example, tavll e time for address valid to ale low. tllpl e time for ale low to psen low. 9
8XC152JA/jb/jc/jd a.c. characteristics (t a e 0 cto a 70 c; v cc e 5v g 10%; v ss e 0v; load capacitance for port 0, ale, and psen e 100 pf; load capacitance for all other outputs e 80 pf) external program and data memory characteristics (note 7, 10) symbol parameter 16.5 mhz variable oscillator unit min max min max 1/tclcl oscillator frequency 3.5 12 mhz 80c152ja/jc 83c152ja/jc 80c152jb/jd 80c152ja/jc-1 3.5 16.5 mhz 83c152ja/jc-1 80c152jb/jd-1 tlhll ale pulse width 81 2tclcl-40 ns tavll address valid to ale low 5 tclcl-55 ns tllax address hold after ale low 25 tclcl-35 ns tlliv ale low to valid 142 4tclcl-100 ns instruction in tllpl ale low to psen low 20 tclcl-40 ns tplph psen pulse width 137 3tclcl-45 ns tpliv psen low to valid 77 3tclcl-105 ns instruction in tpxix input instruction 0 0 ns hold after psen tpxiz input instruction 35 tclcl-25 ns float after psen taviv address to valid 198 5tclcl-105 ns instruction in tplaz psen low to address 10 10 ns float trlrh rd pulse width 263 6tclcl-100 ns twlwh wr pulse width 263 6tclcl-100 ns trldv rd low to valid 138 5tclcl-165 ns data in trhdx data hold after rd 00 ns trhdz data float after rd 51 2tclcl-70 ns tlldv ale low to valid 335 8tclcl-150 ns data in tavdv address to valid 380 9tclcl-165 ns data in tllwl ale low to rd or 132 232 3tclcl-50 3tclcl a 50 ns wr low tavwl address to rd or 112 4tclcl-130 ns wr low tqvwx (8) data valid to wr 196 6tclcl-167 ns transition twhqx data hold after wr 10 tclcl-50 ns trlaz rd low to address 0 0 ns float twhlh rd or wr high to 20 100 tclcl-40 tclcl a 40 ns ale high 10
8XC152JA/jb/jc/jd external program memory read cycle 270431 8 external data memory read cycle 270431 9 11
8XC152JA/jb/jc/jd external data memory write cycle 270431 10 external clock drive symbol parameter min max units 1/tclcl oscillator frequency 3.5 16.5 mhz tchcx high time 20 ns tclcx low time 20 ns tclch rise time 20 ns tchcl fall time 20 ns external clock drive waveform 270431 11 12
8XC152JA/jb/jc/jd local serial channel timingeshift register mode symbol parameter 16.5 mhz variable oscillator units min max min max txlxl serial port clock cycle 727 12tclcl ns time tqvxh output data setup to 473 10tclcl-133 ns clock rising edge txhqx output data hold after 4 2tclcl-117 ns clock rising edge txhdx input data hold after 0 0 ns clock rising edge txhdv clock rising edge to 473 10tclcl-133 ns input data valid shift register mode timing waveforms 270431 12 a.c. testing: input, output waveforms 270431 13 ac inputs during testing are driven at v cc b 0.5 for a logic ``1'' and 0.45v for a logic ``0''. timing measurements are made at v ih min for a logic ``1'' and v il max for a logic ``0''. float waveform 270431 14 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, and begins to float when a 100 mv change from the loaded v oh /v ol level occurs i ol /i oh t g 20 ma. 13
8XC152JA/jb/jc/jd global serial port timingseinternal baud rate generator symbol parameter 16.5 mhz (baud e 0) variable oscillator unit min max min max hbtjr allowable jitter on 0.0375 (0.125 c m s the receiver for (/2 (baud a 1) c bit time (manchester 8tclcl) encoding only) b 25 ns fbtjr allowable jitter on 0.10 (0.25 c m s the receiver for one (baud a 1) c full bit time (nrzi 8tclcl) and manchester) b 25 ns hbtjt jitter of data from g 10 g 10 ns transmitter for (/2 bit time (manchester encoding only) fbtjt jitter of data from g 10 g 10 ns transmitter for one full bit time (nrzi and manchester) drtr data rise time for 20 20 ns receiver (11) dftr data fall time for 20 20 ns receiver (12) gsc receiver timings (internal baud rate generator) 270431 15 14
8XC152JA/jb/jc/jd gsc transmit timings (internal baud rate generator) 270431 16 global serial port timingseexternal clock symbol parameter 16.5 mhz variable oscillator unit min max min max 1/ecbt gsc frequency with an 2.4 0.009 f osc c 0.145 mhz external clock ech external clock high 170 2tclcl ns a 45 ns ecl (13) external clock low 170 2tclcl ns a 45 ns ecrt external clock rise 20 20 ns time (11) ecft external clock fall 20 20 ns time (12) ecdvt external clock to data ns valid out - transmit 150 150 (to external clock negative edge) ecdht external clock data ns hold - transmit 0 0 (to external clock negative edge) ecdsr external clock data 45 45 ns set-up - receiver (to external clock positive edge) ecdhr external clock to data 50 50 ns hold - receiver (to external clock positive edge) 15
8XC152JA/jb/jc/jd gsc timings (external clock) 270431 17 notes: 1. n.c. pins on plcc package may be connected to internal die and should not be used in customer applications. 2. it is recommended that both pin 3 and pin 33 be grounded for plcc devices. 3. ``typicals'' are based on samples taken from early manufacturing lots and are not guaranteed. the measurements were made with v cc e 5v at room temperature. 4. capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1- to-0 transitions during bus operations. in the worst cases (capacitive loading l 100 pf), the noise pulse on the ale pin may exceed 0.8v. in such cases it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. 5. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v cc specifi- cation when the address bits are stabilizing. 6. i cc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl e 5 ns, v il e v ss a 0.5v, v ih e v cc b 0.5v; xtal2 n.c.; port 0 pins connected to v cc . ``operating'' current is measured with ea connected to v cc and rst connected to v ss . ``idle'' current is measured with ea connected to v ss , rst connected to v cc and gsc inactive. 7. the specifications relating to external data memory characteristics are also applicable to dma operations. 8. tqvwx should not be confused with tqvwx as specified for 80c51bh. on 80c152, tqvwx is measured from data valid to rising edge of wr . on 80c51bh, tqvwx is measured from data valid to falling edge of wr . see timing diagrams. 9. this value is based on the maximum allowable die temperature and the thermal resistance of the package. 10. all specifications relating to external program memory characteristics are applicable to: epsen for psen port 5 for port 0 port 6 for port 2 when eben is at a logical 1 on the 80c152jb/jd. 11. same as tclch, use external clock drive waveform. 12. same as tchcl, use external clock drive waveform. 13. when using the same external clock to drive both the receiver and transmitter, the minimum ecl spec effectively becomes 195 ns at all frequencies (assuming 0 ns propagation delay) because ecdvt (150 ns) plus ecdsr (45 ns) re- quirements must also be met (150 a 45 e 195 ns). the 195 ns requirement would also increase to include the maximum propagation delay between receivers and transmitters. 16
8XC152JA/jb/jc/jd design notes within the 8xc152 there exists a race condition that may set both the rdn and ae bits at the end of a valid reception. this will not cause a problem in the application as long as the following steps are followed: enever give the receive error interrupt a higher priority than the valid reception interrupt edo not leave the valid reception interrupt service routine when ae is set by using a reti instruction until ae is cleared. to clear ae set the gren bit, this enables the receiver. if the user desires that the receiver remain disabled, clear gren after setting it before leaving the interrupt service routine. eif the ae bit is checked by user software in response to a valid reception interrupt, the status of ae should be considered invalid. the race condition is dependent upon both the temperature that the device is currently operating at and the processing the device received during the wafer fabrication. when the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. data sheet revision summary the following represent the key differences between the ``-003'' and the ``-002'' version of the 80c152/83c152 data sheet. please review this summary carefully. 1. removed minimum gsc frequency spec when used with an external clock. 2. change figure ``external program memory read cycle'' to show port 0/port 5 address floating after psen goes low. 3. added design note on terminating idle with reset. 4. added status of psen during power down mode to table 3. 5. moved all notes to back of data sheet. 6. changed microcomputer to microcontroller. 7. added external oscillator start-up capacitance note. the following represent the key differences between the ``-002'' and the ``-001'' version of the 80c152/ 83c152 data sheet. please review this summary carefully. 1. status of data sheet changed from ``advanced'' to ``preliminary''. 2. 80c152jc, 83c152jc, and 80c152jd were added. 3. added ae/rdn design note. 4. this revision summary was added. 5. note y 13 was added (effective ecl spec at higher clock rates). 6. table y 2 changed to table y 3 (status of pins during idle/power down). 7. current table y 2 was added (ja vs. jb vs. jc vs. jd matrix). 8. transmit jitter spec changed from g 35 ns and g 70 ns to g 10 ns. 17

▲Up To Search▲

Price & Availability of 8XC152JA

	To Download 8XC152JA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .